Analog-to-digital converters (ADCs) utilize delta-sigma modulators for the purpose of providing high resolution data conversion. These modulators utilize a plurality of over-sampling techniques in order to facilitate this data conversion. Typically, there is provided an input switching network that is operable to sample a voltage input in a first phase onto an input sampling capacitor. In a second phase, this stored charge is transferred or “dumped” onto the input of an integrator which is formed from an amplifier and an feedback capacitor, this transferring the charge to the feedback capacitor. The other input of the amplifier is connected to ground. There is provided another switched capacitor or sampling network that is operable to sample the output signal of the modulator and provide a feedback to the integrator in the form of charge packets. This is facilitated by sampling a reference voltage onto a feedback sampling capacitor and then dumping the charge from this capacitor onto the input of the integrator for transfer to the feedback capacitor. The gain of this modulator is the ratio between the amount of charge transferred from the input sampling capacitor to the feedback capacitor to the amount of charge transferred from the feedback sampling capacitor to the feedback capacitor during the comparator decision cycle. Gain adjustment is facilitated by varying the amount of charge transferred onto the feedback capacitor as a result of sampling the input voltage onto the input sampling capacitor relative to the amount of charge transferred onto the integrating capacitor as a result of sampling a reference voltage onto the feedback sampling capacitor. By either varying the size of the feedback capacitor or the size of the input capacitor or affecting the amount of charge transferred to the integrator from both of those capacitors, the gain can be changed.